Computer implemented method for determining intrinsic parameter in a stacked nanowires MOSFET

ABSTRACT

Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising N w  nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps:
         measuring the following parameters of the MOSFET:
           number of stacked nanowires/nanosheets N W ,   width W W,i , of the nanowire/nanosheet number i, i being an integer from 1 to N W ,   thickness of the nanowire/nanosheet H W,i , number i, i being an integer from 1 to N W ,   corner radius R W,i  of the nanowire/nanosheet number i, i being an integer from 1 to N W , R W,i ;   
           calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage ϕ T  given by ϕ T =k B T/q;   measuring the total gate capacitance for a plurality of gate voltages;   determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowires/nanosheets MOSFET.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to U.S. Provisional Patent ApplicationNo. 62/429,212, filed Dec. 2, 2016, the entire contents of which isincorporated herein by reference in its entirety.

FIELD

This invention relates to a computer implemented method for determiningat least one intrinsic parameter in stacked nanowires/nanosheetsgate-all-around (GAA) MOSFETs (Metal Oxide Semiconductor Field EffectTransistors). A stacked nanowires/nanosheets GAA MOSFET is a transistorcomprising at least two wires/sheets, each wire/sheet being surroundedby an oxide layer, the oxide layers being embedded by a common gate.

BACKGROUND

Stacked nanowires/nanosheets gate-all-around MOSFET is a good candidateto replace FinFET for sub-7 nm CMOS nodes. Each nanowire/nanosheet canhave a shape from cylindrical nanowire to nanosheet with wide widthdepending of the applications: low power to high speed applications.However, there is currently no calculation method to reproduce theelectrical characteristics of these devices. As a consequence, tools arenot available to characterize intrinsic properties, to design integratedcircuits on CMOS technology using GAA transistors architectures encasingstacked nanowires MOSFET, to optimize the device architecture withregard to the consumption, performance, and surface technology targetsof the circuits.

SUMMARY

An aspect of the invention aims at providing a tool for determining atleast one intrinsic parameter of a stacked nanowires/nanosheets MOSFET,such as the equivalent thickness gate, interface states, the gate oxidepermittivity, or the carrier mobility by using surface potentials, draincurrent and charges, which is robust, accurate and with low computationtime. An intrinsic parameter may be defined as a parameter which cannotbe measurable directly (e.g., by standard, known measurements used inmicroelectronics). According to the known in the art solution, the useof methods for other MOSFET architectures like bulk MOSFET do not allowto determine accurately the surface potentials and by consequence thechannel current and charges in the case of stacked nanowires/nanosheetsGAA MOSFET. As a consequence, these other methods will introducesignificant errors on intrinsic parameters.

To that purpose, a first aspect of the invention concerns a computerimplemented method for determining at least one intrinsic parameter of astacked nanowires/nanosheets MOSFET Then, these intrinsic parameters areused to reproduce electrical characteristics in all biasing with acomputer associated to a dedicated set of equations, such as drainoutput current versus gate and drain voltages. These ones are used tosimulate integrated circuits with many transistors, where the layout ofeach transistor can be adapted to optimize its electrical propertieswith respect to circuit performance and power consumption. Typically, anintegrated circuit designer can choose the optimal transistor sizesneeded for a circuit. But without sufficient accuracy of the intrinsicparameters, the device characteristics cannot be correctly evaluated bysimulations. Consequently, the circuit optimization would fail;knowledge of intrinsic parameter(s) is thus necessary for integratedcircuit simulations and transistor design optimizations.

The stacked nanowires/nanosheets MOSFET comprises N_(w) nanowires and/ornanosheets, each nanowire/nanosheet being surrounded in an oxide layer,the oxide layers being embedded in a common gate, wherein the methodcomprises the following steps:

-   -   measuring by at least one imaging method the following        geometrical parameters of the MOSFET:        -   the number of stacked nanowires/nanosheets N_(W),        -   the width W_(W,i), of the nanowire/nanosheet number i, i            being an integer starting from 1 to N_(W),        -   the thickness of the nanowire/nanosheet H_(W,i), number i, i            being an integer starting from 1 to N_(W),        -   the corner radius R_(W,i) of the nanowire/nanosheet number            i, i being an integer starting from 1 to N_(W), R_(W,i);    -   calculating, using a physical processor and the measured        geometrical parameters, a surface potential x normalized by a        thermal voltage ϕ_(T) given by ϕ_(T)=k_(B)T/q;    -   measuring electrically the total gate capacitance for several        gate voltage;    -   determining, using the measured total gate capacitance and the        calculated normalized surface potential, the intrinsic parameter        of the stacked nanowires/nanosheets MOSFET.

The method enables to define unique surface potentials for reducingcomputing time, even if the surface potential is not constant around thenanowire.

According to the method, a unique equivalent surface potential isconsidered even if the surface potential is not constant around eachnanowire. To that purpose, each nanowire is cut in three parts:

-   -   a center part similar to a symmetric double-gate MOSFET;    -   2 corners parts, similar to a quasi-cylindrical nanowire.

The method may then comprise the following steps:

-   -   calculate the total channel width (e.g., effective width) of        stacked nanowire MOSFET;    -   defining geometrical variables for surface potential        calculation;    -   finding analytical solutions for the surface potentials along        the channel;    -   finding analytical formulations of current and charges for        unique or stacked nanowires with width variations.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic representation of a stacked nanowires/nanosheetsGAA MOSFET to which a method according to one embodiment of theinvention may be applied.

FIG. 2 is a cross-section view of the stacked nanowires/nanosheet GAAMOSFET of FIG. 1.

FIG. 3 is an enlarged view of a nanowire/nanosheet of the stackednanowires/nanosheets GAA MOSFET of FIGS. 1 and 2.

FIG. 4 represents the steps of a method according to one embodiment ofthe invention.

FIG. 5(a) represents the evolution of gate capacitance versus gatevoltage of a nanowire GAA MOSFET comprising a unique nanowire with acylindrical section, obtained by a method according to one embodiment ofthe invention and by a simulation of the prior art.

FIG. 5(b) represents the evolution of gate capacitance versus gatevoltage of a nanowire GAA MOSFET comprising a unique nanowire with asquare section with rounded corners, obtained by a method according toone embodiment of the invention and by a simulation of the prior art.

FIG. 6(a) represents the evolution of gate capacitance versus gatevoltage of a nanowire GAA MOSFET comprising a unique nanowire with asquare section obtained by a method according to one embodiment of theinvention and by a simulation of the prior art.

FIG. 6(b) represents the evolution of gate capacitance versus gatevoltage of a nanowire GAA MOSFET comprising a unique nanosheet with arectangular section, obtained by a method according to one embodiment ofthe invention and by a simulation of the prior art.

FIG. 7(a) represents the evolution of gate capacitance versus gatevoltage of a nanowire GAA MOSFET comprising a unique nanosheet with arectangular section and rounded corners obtained by a method accordingto one embodiment of the invention and by a simulation of the prior art.

FIG. 7(b) represents the evolution of gate capacitance versus gatevoltage, of another nanowire GAA MOSFET comprising a unique nanosheetwith a rectangular section and rounded corners for three width values,obtained by a method according to one embodiment of the invention and bya simulation of the prior art.

FIG. 8(a) represents a stacked nanosheet GAA MOSFET to which a methodaccording to one embodiment of this invention is applied.

FIG. 8(b) represents the evolution of gate capacitance versus gatevoltage, of the stacked nanowire GAA MOSFET of FIG. 8(a), obtained by amethod according to one embodiment of the invention and by a simulationof the prior art.

FIG. 9(a) represents a single nanosheet GAA MOSFET to which a methodaccording to one embodiment of this invention is applied.

FIG. 9(b) represents the evolution of drain current versus gate voltage,of the nanosheet GAA MOSFET of FIG. 9(a), obtained by a method accordingto one embodiment of the invention and by a simulation of the prior art.

FIG. 10(a) represents the evolution of current versus voltage gate, inlinear regime, of a single nanosheet GAA MOSFET for several values ofnanosheet width W_(W), obtained by a method according to one embodimentof the invention and by a simulation of the prior art.

FIG. 10(b) represents the evolution of current versus voltage gate, insaturation regime, of a single nanosheet GAA MOSFET for several valuesof nanosheet width W_(W), obtained by a method according to oneembodiment of the invention and by a simulation of the prior art.

FIG. 11(a) represents a single nanosheet GAA MOSFET to which a methodaccording to one embodiment of the invention is applied.

FIG. 11(b) represents total gate capacitance versus gate voltage insaturation regime of the MOSFET of FIG. 11(a), when obtained by a methodaccording to one embodiment of the invention and according to the priorart.

FIG. 12(a) represents gate to source capacitance versus gate voltage insaturation of the MOSFET of FIG. 11(a), obtained by a method accordingto one embodiment of the invention and according to the prior art.

FIG. 12(b) represents gate to drain capacitance versus gate voltage insaturation of the MOSFET of FIG. 11(a), obtained by a method accordingto one embodiment of the invention and according to the prior art.

FIG. 13(a) represents a stacked nanosheet GAA MOSFET to which a methodaccording to one embodiment of the invention is applied.

FIG. 13(b) represents channel current versus gate voltage in linearregime with logarithm scale, of the MOSFET of FIG. 13(a), obtained by amethod according to one embodiment of the invention and according to theprior art.

FIG. 14(a) represents channel current versus gate voltage in linearregime with linear scale, of the MOSFET of FIG. 13(a), determined by amethod according to one embodiment of the invention and according to theprior art.

FIG. 14(b) represents channel current versus gate voltage in saturationregime with linear scale of the MOSFET of FIG. 13(a), determined by amethod according to one embodiment of the invention and according to theprior art.

FIG. 15(a) represents a stacked nanosheet GAA MOSFET to which a methodaccording to one embodiment of the invention is applied.

FIG. 15(b) represents the total gate capacitance versus gate voltage insaturation regime of the MOSFET of FIG. 15(a), determined by a methodaccording to one embodiment of the invention and according to the priorart.

FIG. 16(a) represents the gate to source capacitance versus gate voltagein saturation regime of the MOSFET of FIG. 15(a), determined by a methodaccording to one embodiment of the invention and according to the priorart.

FIG. 16(b) represents the gate to drain capacitance versus gate voltagein saturation regime of the MOSFET of FIG. 15(a), determined by a methodaccording to one embodiment of the invention and according to the priorart.

FIG. 17 is a schematic representation of one embodiment of the methodaccording to one embodiment of the invention.

DETAILED DESCRIPTION

FIGS. 1 and 2 schematically represent a stacked nanowire MOSFET to whicha method according to one embodiment of the invention may be applied todetermine surface potential in the transistor.

This stacked nanowires/nanosheets GAA MOSFET 10 comprises at least onenanowire 11 forming a drain, a source and a channel. All drains are samepotential. All sources are same potential. Each nanowire 11 issurrounded by an oxide film 12. The stacked nanowire MOSFET alsocomprises a common gate 13 surrounding the oxide layers.

FIG. 3 represents an enlarged view of a nanowire 11 of the stackednanowire MOSFET of FIGS. 1 and 2.

Each nanowire may have different shapes: it may have a rectangularsection with rounded corners (nanosheet), a cylindrical section(nanowire) or a square section (nanowire). Each nanowire/nanosheet i hasa width W_(w,i) and a height H_(w,i). In case of rounded corners, eachrounded corner has a radius R_(c,i).

A method according to one embodiment of the invention will now bedescribed by reference to FIGS. 4 to 15(b).

This method may be implemented by a computer comprising at least oneinterface, at least one physical processor and a non-transitory memory(also broadly referred to as a non-transitory machine readable orstorage medium). The computer is a special purpose computer as it isprogrammed to perform the specific calculation steps of the method. Thenon-transitory memory is encoded or programmed with specific codeinstructions for carrying out the calculation steps. In particular,calculation steps described above can be carried out using codeinstructions embedded in the non-transitory memory. The non-transitorymemory is arranged in communication with the at least one physicalprocessor so that the at least one physical processor, in use, reads andexecutes the specific code instructions embedded in the non-transitorymemory. The interface of the special purpose computer is arranged incommunication with the at least one physical processor and receivesinput parameters that are processed by the at least one physicalprocessor.

Having described and illustrated the principles of the invention withreference to various embodiments, it will be recognized that the variousembodiments can be modified in arrangement and detail without departingfrom such principles. It should be understood that the programs,processes, or methods described herein are not related or limited to anyparticular type of computing environment, unless indicated otherwise.Various types of specialized computing environments may be used with orperform operations in accordance with the teachings described herein.Elements of embodiments shown in software may be implemented in hardwareand vice versa.

The devices, processors or processing devices described herein may beconfigured to execute one or more sequences of one or more instructionscontained in a main memory or a computer readable medium. Execution ofthe sequences of instructions contained in a main memory or a computerreadable medium causes the processor to perform at least some of theprocess steps described herein. One or more processors in amulti-processing arrangement may also be employed to execute thesequences of instructions contained in a main memory or a computerreadable medium. In alternative embodiments, hard-wired circuitry may beused in place of or in combination with software instructions. Thus,embodiments are not limited to any specific combination of hardwarecircuitry and software.

The term “computer readable medium” as used herein refers to anyphysical medium that participates in providing instructions to aprocessor for execution. Such a medium may take many forms, includingbut not limited to, non-volatile media, volatile media, and transmissionmedia. Non-volatile media include, for example, optical or magneticdisks. Volatile media include dynamic memory. Transmission media includecoaxial cables, copper wire and fiber optics. Common forms ofcomputer-readable media include, for example, a floppy disk, a flexibledisk, hard disk, magnetic tape, any other magnetic medium, a CD-ROM,DVD, any other optical medium, punch cards, paper tape, any otherphysical medium with patterns of holes, a RAM, a PROM, and EPROM, aFLASH-EPROM, any other memory chip or cartridge, or any other mediumfrom which a computer can read.

Various forms of computer readable media may be involved in carrying oneor more sequences of one or more instructions to the at least oneprocessor for execution.

It will be appreciated that the method described herein represents asolution to the technological problem currently faced by skilledartisans in designing gate transistors encasing stacked nanowires MOSFETthat satisfy consumption, performance, and/or surface technologyconstraints. The method described herein is greatly beneficial as itpermits determination of at least one intrinsic parameter of a stackednanowires/nanosheets MOSFET.

The method enables to determine the surface potential in the channel atsource and/or drain side in the stacked nanowires/nanosheet GAA MOSFETof FIGS. 1 to 3.

The determination of surface potential at the source side and thedetermination of surface potential at the drain side are carried outwith the same procedure, the only difference between both determinationbeing the bias of the considered electrode (source or drain). In thefollowing, we will thus use an electrode bias V_(x) that correspondseither to source or to drain bias.

Input Parameters:

The method comprises first a step 101 of receiving, using the interface,a set of input parameters describing the effective geometry of thestacked nanowire MOSFET 10 and the process device parameters, theeffective biases V_(g) and V_(x) on the gate and the source or drain,and the temperature. The set of input parameters received by theinterface is summarized in Tables 1, 2 and 3 below.

The definitions of all geometrical parameters are given in the tables 1and 2.

TABLE 1 Effective device geometrical parameters Notation UnitDescription N_(w) — Number of stacked nanowires/nanosheets L m Effectivegate length H_(w,i) m Effective thickness of the nanowire/nanosheetnumber i (i = 1 to N_(w)) W_(w,i) m Effective width of thenanowire/nanosheet number i (i = 1 to N_(w)) R_(c,i) m Effective cornerradius of the nanowire/nanosheet number i (i = 1 to N_(w)) T_(ox) mEffective gate dielectric equivalent oxide thickness

TABLE 2 Process device parameters. Notation Unit Description ε_(ox) F/mGate dielectric permittivity ε_(ch) F/m Channel dielectric permittivityn_(ch) m⁻³ Intrinsic channel doping concentration Δϕ_(m) eV Gateworkfunction with respect to the midgap level of thenanowires/nanosheets

The effective biases on the electrodes and the channel temperature aregiven in the table 3.

TABLE 3 Effective biases and temperature. Notation Unit DescriptionV_(g) V Effective gate bias V_(x) V Effective source or drain bias T °KChannel temperature

Table 4 provides all physical constants used in the method.

TABLE 4 Physical constants. Notation Unit Description k_(B) J.K⁻¹Boltzmann constant q C Elementary charge π — Mathematical constant =3.141592654

Calculation of Normalized Quantities:

The method may then comprise a step 102 of calculation of normalizedquantities:

Normalized gate potential: x_(g)=(V_(g)-Δϕ_(m))/ϕ_(T)

Normalized source or drain potential: x_(n)=V_(x)/ϕ_(T)

Normalized surface potential: x=φ_(s)/ϕ_(T)

Normalized charge: q=Q/(C_(ox)·ϕ_(T))

With Or the thermal voltage given by: ϕ_(T)=k_(B)T/q

Even if this step is not mandatory, it enables to reduce the number ofvariables/parameters in the equations. So, with this step, the computingtime is improved.

Determination of the Potential Surface:

The method is based on the resolution, using the physical processor, ofthe following equation:(x _(g) −x)² +B _(sp)·(x _(g) −x)=Δ_(f)·exp(x−x _(n))  [Eq. 1]

Where x is the surface potential normalized by a thermal voltage ϕ_(T)given by ϕ_(T)=k_(B)T/q, B_(sp) and Δ_(f) are constants depending on thegeometry of the stacked nanowires MOSFET, x_(g) is an effective gatebias.

Determination of Constants B_(sp) and Δ_(f)

To do that, the method comprises a step 103 of determining, using thephysical processor, constants B_(sp) and Δ_(f) according to theparameters received by the interface.

The constants B_(sp) and Δ_(f) are given by:

$\begin{matrix}{{B_{sp} = \frac{4 \cdot ɛ_{ch}}{H_{sp} \cdot C_{ox}^{\prime}}}{\Delta_{f} = \frac{2 \cdot q \cdot n_{ch} \cdot ɛ_{ch}}{\phi_{T} \cdot C_{ox}^{\prime 2}}}} & \left\lbrack {{Eq}.\mspace{14mu} 2} \right\rbrack\end{matrix}$

Where C_(ox)′ is a total equivalent gate oxide capacitance of thestacked nanowires/nanosheets GAA MOSFET and H_(sp) is a total equivalentfilm thickness of the stacked nanowires/nanosheets GAA MOSFET.

The method comprises then a step 104 of calculating, using the physicalprocessor, the total equivalent gate oxide capacitance C_(ox)′ and thetotal equivalent film thickness H_(sp) of the stackednanowires/nanosheets GAA MOSFET.

To that purpose, each nanowire i is partitioned in three parts asillustrated on FIG. 3:

-   -   A central part that will be treated as a symmetrical double gate        transistor;    -   two corners parts on each side of the central part, each corner        part being considered as a cylindrical transistor.

Each corner part has a width H_(w,i)/2.

Some specific cases can be noted and summarized by the table 5.

TABLE 5 Specific cases of nanowires/nanosheet structures. Case R_(c, i)W_(w, i) Cylindrical nanowire = H_(w, i)/2 = H_(w, i) Square nanowire =0 = H_(w, i) Cylindrical nanosheet = H_(w, i)/2 — Rectangular nanosheet= 0 —

The method comprises first a step 105 of computing, using the physicalprocessor, for each nanowire or nanosheet, an effective channel widthW_(effnw,i) corresponding to the perimeter of a transversal section ofeach nanowire. The effective channel width W_(effnw,i) may be given by:W _(effnw,i)=2·(W _(W,i) −H _(W,i))+2·π·R _(c,i)+2·(H _(W,i)−2·R_(c,i))  [Eq. 3]

The method comprises then a step 106 of computing, for each oxide layer,using the physical processor, an effective gate oxide width W_(oxnw,i),corresponding to the perimeter of a transversal section of each oxidelayer. The effective gate oxide width W_(oxnw,i) may be given by:

$\begin{matrix}{\mspace{79mu}{{W_{{oxnw},i} = {{4 \cdot \left( {\frac{2 \cdot T_{ox} \cdot {dS}_{0,i}}{\ln\left( \frac{r_{\max,i}^{\prime}}{r_{\min,i}^{\prime}} \right)} + H_{W,i} - {2 \cdot R_{{clim},i}}} \right)} + W_{{effcent},i}}}\mspace{20mu}{{With}\text{:}}\mspace{20mu}{R_{{clim},i} = {\max\left( {R_{c,i},\frac{T_{ox}}{2}} \right)}}\mspace{20mu}{r_{0,i} = {R_{{clim},i} + \frac{T_{ox}}{2}}}\mspace{20mu}{{dR}_{{clim},i} = {R_{{clim},i} - R_{c,i}}}\mspace{20mu}{r_{{0\min},i} = \sqrt{r_{0,i}^{2} + {dR}_{{clim},i}^{2}}}\mspace{20mu}{r_{{0\max},i} = {{\left( {\sqrt{2} - 1} \right) \cdot {dR}_{{clim},i}} + r_{0,i}}}\mspace{20mu}{\theta_{0,i} = {\arctan\left( \frac{r_{0,i} - {dR}_{{clim},i}}{r_{0,i} + {dR}_{{clim},i}} \right)}}\mspace{20mu}{{lr}_{0,i} = {\ln\left( \frac{{dR}_{{clim},i} + r_{{0\min},i}}{r_{0,i}} \right)}}\mspace{20mu}{S_{0,i} = {{r_{0,i} \cdot {lr}_{0,i}} + {\frac{r_{{0\min},i} + {2 \cdot r_{{0\max},i}}}{3} \cdot \theta_{0,i}}}}{{dS}_{0,i} = {{llr}_{0,i} + {\frac{1}{3} \cdot \left( {\frac{r_{0,i}}{r_{{0\min},i}} + 2} \right) \cdot \theta_{0,i}} + {\frac{2}{3} \cdot \left( {r_{{0\max},i} - r_{{0\min},i}} \right) \cdot \frac{{dR}_{{clim},i}}{r_{{0\min},i}^{2}}}}}\mspace{20mu}{r_{\min,i}^{\prime} = {{{dS}_{0,i} \cdot \left( {R_{{clim},i} - r_{0,i}} \right)} + S_{0,i}}}\mspace{20mu}{r_{\max,i}^{\prime} = {r_{\min,i}^{\prime} + {{dS}_{0,i} \cdot T_{ox}}}}}} & \left\lbrack {{Eq}.\mspace{14mu} 4} \right\rbrack\end{matrix}$

The method comprises then a step 107 of computing, using the physicalprocessor, an equivalent normalized gate oxide C_(oxnw,i) for eachnanowire. The equivalent normalized gate oxide C_(oxnw,i) is given by:

$\begin{matrix}{C_{{oxnw},i} = {\frac{ɛ_{ox}}{T_{ox}} \cdot \frac{W_{{oxnw},i}}{W_{{effnw},i}}}} & \left\lbrack {{Eq}.\mspace{14mu} 5} \right\rbrack\end{matrix}$

The method comprises then a step 108 of computing, using the physicalprocessor, an equivalent semiconductor film thickness H_(spnw,i), foreach nanowire:

$\begin{matrix}{H_{{spnw},i} = {{\frac{W_{{effcent},i}}{W_{{effnw},i}} \cdot H_{W,i}} + {\frac{2 \cdot W_{{effcorn},i}}{W_{{effnw},i}} \cdot \frac{2 \cdot H_{W,i}}{\pi} \cdot \left( {{\ln\left( {\left( {1 - {2 \cdot \frac{R_{c,i}}{H_{W,i}}}} \right) + \sqrt{1 + \left( {1 - {2 \cdot \frac{R_{c,i}}{H_{W,i}}}} \right)^{2}}} \right)} + {{\frac{\begin{matrix}{\sqrt{1 + \left( {1 - {2 \cdot \frac{R_{c,i}}{H_{W,i}}}} \right)^{2}} +} \\{2 \cdot \left( {{\left( {\sqrt{2} - 1} \right) \cdot \left( {1 - {2 \cdot \frac{R_{c,i}}{H_{W,i}}}} \right)} + 1} \right)}\end{matrix}}{3} \cdot a}\;{\tan\left( \frac{\frac{R_{c,i}}{H_{W,i}}}{1 - \frac{R_{c,i}}{H_{W,i}}} \right)}}} \right)}}} & \left\lbrack {{Eq}.\mspace{14mu} 6} \right\rbrack\end{matrix}$

The method comprises then a step 109 of computing, using the physicalprocessor, a total effective width of the structure W_(eff) given by:

$\begin{matrix}{W_{eff} = {\sum\limits_{i = 1}^{N_{w}}W_{{effnw},i}}} & \left\lbrack {{Eq}.\mspace{14mu} 7} \right\rbrack\end{matrix}$

The method comprises then a step 110 of computing, using the physicalprocessor an total equivalent normalized gate oxide C_(ox)′ given by:

$\begin{matrix}{C_{ox}^{\prime} = {\sum\limits_{i = 1}^{N_{w}}{\frac{W_{{effnw},i}}{\sum\limits_{i = 1}^{N_{w}}W_{{effnw},i}} \cdot C_{{oxnw},i}^{\prime}}}} & \left\lbrack {{Eq}.\mspace{14mu} 8} \right\rbrack\end{matrix}$

The method also comprises a step 111 of computing, using the physicalprocessor, an equivalent semiconductor film thickness H_(sp) given by:

$\begin{matrix}{H_{sp} = {\sum\limits_{i = 1}^{N_{w}}{\frac{W_{{effnw},i}}{\sum\limits_{i = 1}^{N_{w}}W_{{effnw},i}} \cdot H_{{spnw},i}}}} & \left\lbrack {{Eq}.\mspace{14mu} 9} \right\rbrack\end{matrix}$

Constants B_(sp) and ϕ_(f) are then determined using the physicalprocessor during step 103:

The constants B_(sp) and Δ_(f) are given by:

$\begin{matrix}{{B_{sp} = \frac{4 \cdot ɛ_{ch}}{H_{sp} \cdot C_{ox}^{\prime}}}{\Delta_{f} = \frac{2 \cdot q \cdot n_{ch} \cdot ɛ_{ch}}{\phi_{T} \cdot C_{ox}^{\prime 2}}}} & \left\lbrack {{Eq}.\mspace{14mu} 10} \right\rbrack\end{matrix}$

The method comprises then a step 104 of determining a normalized surfacepotential x that solve the following equation:

$\begin{matrix}{{{\left( {x_{g} - x} \right)^{2} + {B_{sp} \cdot \left( {x_{g} - x} \right)}} = {\Delta_{f} \cdot {\exp\left( {x - x_{n}} \right)}}}{{{With}\mspace{14mu}\Delta_{f}} = {{\frac{2 \cdot q \cdot n_{ch} \cdot ɛ_{ch}}{\Phi_{T} \cdot C_{ox}^{\prime 2}}\mspace{14mu}{and}\mspace{14mu} B_{sp}} = \frac{4 \cdot ɛ_{ch}}{H_{sp} \cdot C_{ox}^{\prime}}}}} & \left\lbrack {{Eq}.\mspace{14mu} 11} \right\rbrack\end{matrix}$

This equation may be solved by using a successive error calculationsimilarly to the work of T. L. Chen and G. Gildenblat (publication inSolid-State Electronics, vol. 45, 2001).

According to this embodiment, a normalized threshold voltage x_(th) isfirst determined by using the physical processor. The normalizedthreshold voltage x_(th) is given by:

$\begin{matrix}{x_{th} = {{\ln\left( {\phi_{T} \cdot C_{ox}^{\prime 2} \cdot \frac{2 + B_{sp}}{q \cdot n_{ch} \cdot ɛ_{ch}}} \right)} + x_{n}}} & \left\lbrack {{Eq}.\mspace{14mu} 12} \right\rbrack\end{matrix}$

The method comprises then a step of determining a normalized surfacepotential approximation x₀ given by:

$\begin{matrix}{{x_{0} = {{Min\_ func}\left( {x_{0{si}},x_{g},1} \right)}}{{With}\text{:}}{x_{{gt}\; 0} = {x_{g} - x_{th} - 1}}{x_{{gt}\; 0{eff}} = {\frac{1}{2} \cdot \left( {x_{{gt}\; 0} + \sqrt{x_{{gt}\; 0}^{2} + 10}} \right)}}{x_{0{si}} = {x_{n} + {\ln\left( {x_{{gt}\; 0{eff}} \cdot \frac{x_{{gt}\; 0{eff}} + B_{sp}}{\Delta_{f}}} \right)}}}} & \left\lbrack {{Eq}.\mspace{14mu} 13} \right\rbrack\end{matrix}$

${{Min\_ func}\left( {x,\ y,\ a} \right)\mspace{14mu}{can}\mspace{14mu}{be}\mspace{14mu}{defined}\mspace{14mu}{by}\text{:}{Min\_ func}\left( {x,\ y,\ a} \right)} = {\frac{1}{2} \cdot \left( {x + y - \sqrt{\left( {x - y} \right)^{2} + a}} \right)}$

The method comprises then a step of computing, using the physicalprocessor a normalized surface potential xi using a first errorcalculation given by:

$\begin{matrix}{{x_{1} = {x_{0} + \frac{\lambda \cdot a_{s}}{\mu - {\frac{\lambda \cdot b_{s}}{\mu} \cdot \left( {\frac{b_{s}^{2}}{3} - a_{s}} \right)}}}}{{With}\text{:}}{a_{s\; 0} = {x_{g} \cdot \left( {x_{g} + B_{sp}} \right)}}{a_{s\; 1} = {{2 \cdot x_{g}} + B_{sp}}}{a_{s} = {x_{0}^{2} - {a_{s\; 1} \cdot x_{0}} + a_{s\; 0}}}{b_{s} = {{2 \cdot x_{0}} - a_{s\; 1}}}{\alpha = {x_{n} - x_{0} + {\ln\left( \frac{a_{s}}{\Delta_{f}} \right)}}}{\lambda = {a_{s} - b_{s}}}{\mu = {\frac{\lambda^{2}}{\alpha} + \frac{b_{s}^{2}}{2} - a_{s}}}} & \left\lbrack {{Eq}.\mspace{14mu} 14} \right\rbrack\end{matrix}$

The method comprises then a step of computing, using the physicalprocessor, a final normalized surface potential x using a second errorcalculation:

$\begin{matrix}{{x = {x_{1} + \frac{2 \cdot \rho}{\omega + \sqrt{\omega^{2} - {2 \cdot \rho \cdot \left( {2 \cdot \Delta_{f} \cdot {\exp\left( {x_{1} - x_{n}} \right)}} \right)}}}}}{{With}\text{:}}{\omega = {{2 \cdot \left( {x_{g} - x_{1}} \right)} + B_{sp} + {\Delta_{f} \cdot {\exp\left( {x_{1} - x_{n}} \right)}}}}{\rho = {\left( {x_{g} - x_{1}} \right)^{2} + {B_{sp} \cdot \left( {x_{g} - x_{1}} \right)} - {\Delta_{f} \cdot {\exp\left( {x_{1} - x_{n}} \right)}}}}} & \left\lbrack {{Eq}.\mspace{14mu} 15} \right\rbrack\end{matrix}$

The surface potential at the source side x_(s) is then given by:x _(s) =x for x _(n) =x _(n,s) =V _(s)/ϕ_(T)  [Eq. 16]

The surface potential at the drain side x_(d) is then given by:x _(d) =x for x _(n) =x _(n,d) =V _(d)/ϕ_(T)  [Eq. 17]

The method may then comprise a step 112 of determining, using thephysical processor, a channel current and/or a step 113 of determining,using the physical processor, a channel charge thanks to the knowledgeof the surface potential at the source and at the drain side. Channelcurrent and channel charge may be determined by several methods.According to one embodiment, the following method may be used.

Determination of Drain Current:

The method comprises first a step of determining the normalizedinversion charge given by:q _(i) =x _(g) −x  [Eq. 18]

In order to have a symmetrical model when the drain-source are reversed,the charge is considered as being:q _(i) =q _(im)+(x _(m) −x)  [Eq. 19]

Where x_(m) and q_(im) are the mid-point surface potential andinversion, respectively.

$\begin{matrix}{q_{im} = {x_{g} - x_{m}}} & \left\lbrack {{Eq}.\mspace{14mu} 20} \right\rbrack \\{x_{m} = \frac{x_{d} + x_{s}}{2}} & \left\lbrack {{Eq}.\mspace{14mu} 21} \right\rbrack\end{matrix}$

The drain current can be calculated considering the variation of thechannel voltage (or quasi-level Fermi) V_(c) by:

$\begin{matrix}{I_{d} = {{{- W} \cdot \mu \cdot C_{ox}^{\prime} \cdot \phi_{T}^{2} \cdot q_{i}}\frac{{dx}_{n}}{dy}}} & \left\lbrack {{Eq}.\mspace{14mu} 22} \right\rbrack\end{matrix}$

The method comprises then a step of integrating this last equationbetween the source and the drain:

$\begin{matrix}{I_{d} = {{- \frac{W}{L}} \cdot \mu \cdot {\int_{V_{s}}^{V_{d}}{Q_{i}{dV}_{c}}}}} & \left\lbrack {{Eq}.\mspace{14mu} 23} \right\rbrack\end{matrix}$

W, L and μ are the channel width, channel length and the mobility,respectively.

Using normalized units, the drain current calculation becomes:

$\begin{matrix}{I_{d} = {{- \frac{W}{L}} \cdot \mu \cdot C_{ox}^{\prime} \cdot \phi_{T}^{2} \cdot {\int_{x_{n,s}}^{x_{n,d}}{q_{i}{dx}_{n}}}}} & \left\lbrack {{Eq}.\mspace{14mu} 24} \right\rbrack\end{matrix}$

The method comprises then a step of integrating the surface potential:

$\begin{matrix}{I_{d} = {{- \frac{W}{L}} \cdot \mu \cdot C_{ox}^{\prime} \cdot \phi_{T}^{2} \cdot {\int_{x_{s}}^{x_{d}}{q_{i}\frac{{dx}_{n}}{dx}{dx}}}}} & \left\lbrack {{Eq}.\mspace{14mu} 25} \right\rbrack\end{matrix}$

The method comprises then a step of computing the derivate dx_(n)/dx byusing equation [Eq. 1] at x=x_(m).

Using equation [Eq. 1]:

$\begin{matrix}{{\frac{d}{dx}\left( {\left( {x_{g} - x} \right)^{2} + {B_{sp} \cdot \left( {x_{g} - x} \right)}} \right)} = {{\Delta_{f} \cdot \frac{d}{dx}}\left( {\exp\left( {x - x_{n}} \right)} \right)}} & \left\lbrack {{Eq}.\mspace{14mu} 26} \right\rbrack\end{matrix}$

So,

$\begin{matrix}{{{{- 2} \cdot \left( {x_{g} - x} \right)} - B_{sp}} = {\Delta_{f} \cdot \left( {1 - \frac{{dx}_{n}}{dx}} \right) \cdot {\exp\left( {x - x_{n}} \right)}}} & \left\lbrack {{Eq}.\mspace{14mu} 27} \right\rbrack\end{matrix}$

At x=x_(m):

$\begin{matrix}{\chi_{m} = {1 + \frac{{2 \cdot \left( {x_{g} - x_{m}} \right)} + B_{sp}}{\Delta_{f} \cdot \Delta_{m}}}} & \left\lbrack {{Eq}.\mspace{14mu} 28} \right\rbrack \\{with} & \; \\{\Delta_{m} = {\exp\left( {x_{m} - x_{n,m}} \right)}} & \left\lbrack {{Eq}.\mspace{14mu} 29} \right\rbrack\end{matrix}$

x_(nm) is the channel voltage at the mid-point surface potential.

The method comprises then a step of computing Δ_(m), by using equation[Eq. 1], at the mid-point surface potential:(x _(g) −x _(m))² +B _(sp)·(x _(g) −x _(m))=Δ_(f)·exp(x _(m) −x_(n,m))=Δ_(f)·Δ_(m)  [Eq. 30]

The surface potential at the source side:(x _(g) −x _(s))² +B _(sp)·(x _(g) −x _(s))=Δ_(f)·Δ_(s)  [Eq. 31]With:Δ_(s)=exp(x _(s) −x _(n,s))  [Eq. 32]

The surface potential at the drain side:(x _(g) −x _(d))² +B _(sp)·(x _(g) −x _(d))=Δ_(f)·Δ_(d)  [Eq. 33]With:Δ_(d)=exp(x _(d) −x _(n,d))  [Eq. 34]

The method comprises then a step of computing, using the physicalprocessor:

-   -   2x[Eq. 30]-[Eq. 31]-[Eq. 33]        2·x _(m) ² −x _(d) ² −x _(s) ²=Δ_(f)·(2·Δ_(m)−Δ_(d)−Δ_(s))  [Eq.        35]

After some arrangements:

$\begin{matrix}{\Delta_{m} = {\frac{\Delta_{d} + \Delta_{s}}{2} - {\frac{1}{4 \cdot \Delta_{f}} \cdot x_{ds}^{2}}}} & \left\lbrack {{Eq}.\mspace{14mu} 36} \right\rbrack\end{matrix}$

The method comprises then a step of computing the drain currentcalculation [Eq. 25] by using x_(m):

$\begin{matrix}{I_{d} = {{- \frac{W}{L}} \cdot \mu \cdot C_{ox}^{\prime} \cdot \phi_{T}^{2} \cdot \chi_{m} \cdot {\int_{x_{s}}^{x_{d}}{q_{i}{dx}}}}} & \left\lbrack {{Eq}.\mspace{14mu} 37} \right\rbrack\end{matrix}$

The drain current is then expressed by using equation [Eq. 19]:

$\begin{matrix}{I_{d} = {{- \frac{W}{L}} \cdot \mu \cdot C_{ox}^{\prime} \cdot \phi_{T}^{2} \cdot q_{im}^{\prime} \cdot x_{ds}}} & \left\lbrack {{Eq}.\mspace{14mu} 38} \right\rbrack \\{{With}\text{:}} & \; \\{q_{im}^{\prime} = {\chi_{m} \cdot q_{im}}} & \left\lbrack {{Eq}.\mspace{14mu} 39} \right\rbrack\end{matrix}$

Determination of Drain Current in Case of Low Gate Voltage

When the gate voltage is near to the flatband voltage, the values of thesurface potential are very low. The calculation of x_(ds) becomessensitive and is calculated differently.

In general case, the surface potentials at the source and drain sidesare defined by the equation [Eq. 1]:(x _(g) −x _(s))² +B _(sp)·(x _(g) ·x _(s))=Δ_(f)·exp(x _(s) −x_(n,s))  [Eq. 40](x _(g) −x _(d))² +B _(sp)·(x _(g) −x _(d))=Δ_(f)·exp(x _(d) −x_(n,d))  [Eq. 41]

The difference between these two equations is:(x _(g) −x _(d))²−(x _(g) −x _(s))² −B _(sp)·(x _(d) −x_(s))=Δ_(f)·(exp(x _(d) −x _(n,d))−exp(x _(s) −x _(n,s)))  [Eq. 42]So,(x _(ds) −B _(sp)−2·(x _(g) −x _(s)))·x _(ds)=Δ_(f)·Δ_(s)·(exp(x _(ds)−x _(n,ds))−1)  [Eq. 43]With:x _(n,ds) =x _(n,d) −x _(n,s)  [Eq. 44]

When Δ_(f)·Δ_(s) is low, i.e. inferior to 10⁻⁶, the surface potentialdifference x_(ds) cannot be accurately calculated. Consequently, if(Δ_(f)·Δ_(s))<10⁻⁶, the method uses the following approximation:

At low gate voltage:x _(ds) −B _(sp)−2·(x _(g) −x _(s))≈−B _(sp)  [Eq. 45]So,−B _(sp) ·x _(ds)≈Δ_(f)·Δ_(s)·(exp(−x _(n,ds))−1)  [Eq. 46]

Finally:

$\begin{matrix}{x_{ds} \approx {\frac{\Delta_{f} \cdot \Delta_{s}}{B_{sp}} \cdot \left( {1 - {\exp\left( {- x_{n,{ds}}} \right)}} \right)}} & \left\lbrack {{Eq}.\mspace{14mu} 47} \right\rbrack \\{With} & \; \\{\Delta_{s} \approx {\exp\left( x_{g} \right)}} & \left\lbrack {{Eq}.\mspace{14mu} 48} \right\rbrack\end{matrix}$

We have:

$\begin{matrix}{x_{ds} \approx {\frac{\Delta_{f}}{B_{sp}} \cdot {\exp\left( x_{g} \right)} \cdot \left( {1 - {\exp\left( {- x_{n,{ds}}} \right)}} \right)}} & \left\lbrack {{Eq}.\mspace{14mu} 49} \right\rbrack\end{matrix}$

In addition, when x_(g)<0, the channel is in weak inversion. Using [Eq.30], the mid-point inversion charge can be approximated by:

$\begin{matrix}{q_{im} \approx {\frac{\Delta_{f}}{B_{sp}} \cdot \Delta_{m}}} & \left\lbrack {{Eq}.\mspace{14mu} 50} \right\rbrack\end{matrix}$

The effective inversion charge q_(im)′ is given by the equation [eq.39].

Using equation [Eq. 28] and the previous approximation:

$\begin{matrix}{q_{im}^{\prime} \approx {\left( {1 + \frac{{2 \cdot q_{im}} + B_{sp}}{\Delta_{f} \cdot \Delta_{m}}} \right) \cdot q_{im}}} & \left\lbrack {{Eq}.\mspace{14mu} 51} \right\rbrack \\{{So},} & \; \\{q_{im}^{\prime} \approx {q_{im} + \frac{{2 \cdot q_{im}^{2}} + {B_{sp} \cdot q_{im}}}{\Delta_{f} \cdot \Delta_{m}}}} & \left\lbrack {{Eq}.\mspace{14mu} 52} \right\rbrack\end{matrix}$

Using equation [eq. 30], q′_(im) is given by:

$\begin{matrix}{q_{im}^{\prime} \approx {q_{im} + \frac{q_{im}^{2} + {\Delta_{f} \cdot \Delta_{m}^{\prime}}}{\Delta_{f} \cdot \Delta_{m}}} \approx {q_{im} + \frac{q_{im}^{2}}{\Delta_{f} \cdot \Delta_{m}} + 1}} & \left\lbrack {{Eq}.\mspace{14mu} 53} \right\rbrack\end{matrix}$

With q_(im)<<1:q′ _(im)≈1  [Eq. 54]

Determination of Drain Current in Case of Low Drain Voltage x_(Ds)

At low drain voltages, x_(ds) has a low values, its exponential can beapproximated into the equation [Eq. 43] with the first order Taylor'sdevelopment:(x _(ds) −B _(sp)−2·(x _(g) −x _(s)))·x _(ds)=Δ_(f)·Δ_(s)·((1+x_(ds))·exp(−x _(n,ds))−1)  [Eq. 55]After some arrangements:(x _(ds) −A _(ds))·x _(ds)+Δ_(f)·Δ_(s)·(1−exp(−x _(n,ds)))=0  [Eq. 56]With,A _(ds) =B _(sp)+2·(x _(g) −x _(s))+Δ_(f)·Δ_(s)·exp(−x _(n,ds))=0  [Eq.57]

Also with x_(ds)<<A_(ds) and exp(−x_(n,ds))≈1, we find:

$\begin{matrix}{x_{ds} \approx {\frac{\Delta_{f} \cdot \Delta_{s}}{A_{ds}} \cdot \left( {1 - {\exp\left( {- x_{n,{ds}}} \right)}} \right)}} & \left\lbrack {{Eq}.\mspace{14mu} 58} \right\rbrack \\{{With},} & \; \\{A_{ds} = {B_{sp} + {2 \cdot \left( {x_{g} - x_{s}} \right)} + {\Delta_{f} \cdot \Delta_{s}}}} & \left\lbrack {{Eq}.\mspace{14mu} 59} \right\rbrack\end{matrix}$

Determination of Channel Charges:

Total Normalized Inversion Charge q_(inv)

The total inversion charge is obtained by the integration of theinversion charge q_(i) along the channel:

$\begin{matrix}{q_{inv} = {\frac{1}{L} \cdot {\int_{0}^{L}{q_{i}{dy}}}}} & \left\lbrack {{Eq}.\mspace{14mu} 60} \right\rbrack\end{matrix}$

The integration between the surface potentials at the drain and at thesource sides is also given by:

$\begin{matrix}{q_{inv} = {\frac{1}{L} \cdot {\int_{x_{s}}^{x_{d}}{{q_{i} \cdot \frac{dy}{dx}}{dx}}}}} & \left\lbrack {{Eq}.\mspace{14mu} 61} \right\rbrack\end{matrix}$

The method comprises a step of evaluating the reverse of the derivativeof the surface potential x with the position y.

To do this, it is possible to consider that the current in the channeldoesn't depend on the position.

In inversion, the drain current given by the equation [Eq. 38] is equalto drain current:

$\begin{matrix}{I_{d} = {{- W} \cdot \mu \cdot C_{ox}^{\prime} \cdot \phi_{T}^{2} \cdot q_{i} \cdot \frac{{dx}_{n}}{dy}}} & \left\lbrack {{Eq}.\mspace{14mu} 62} \right\rbrack\end{matrix}$

Which is equivalent to:

$\begin{matrix}{{\frac{1}{L} \cdot q_{im}^{\prime} \cdot x_{ds}} = {{q_{i} \cdot \frac{{dx}_{n}}{dy}} = {q_{i} \cdot \frac{{dx}_{n}}{dx} \cdot \frac{dx}{dy}}}} & \left\lbrack {{Eq}.\mspace{14mu} 63} \right\rbrack\end{matrix}$

To simplify the calculation, we use this approximation:

$\begin{matrix}{{q_{i} \cdot \frac{{dx}_{n}}{dx}} \approx {q_{im}^{\prime} + \left( {x_{m} - x} \right)}} & \left\lbrack {{Eq}.\mspace{14mu} 64} \right\rbrack \\{{So},} & \; \\{{\frac{1}{L} \cdot q_{im}^{\prime} \cdot x_{ds}} = {\left( {q_{im}^{\prime} + \left( {x_{m} - x} \right)} \right) \cdot \frac{dx}{dy}}} & \left\lbrack {{Eq}.\mspace{14mu} 65} \right\rbrack\end{matrix}$

After some arrangements:

$\begin{matrix}{\frac{dy}{dx} = {\frac{L}{x_{ds}} \cdot \left( {1 + \frac{x_{m} - x}{q_{im}^{\prime}}} \right)}} & \left\lbrack {{Eq}.\mspace{14mu} 66} \right\rbrack\end{matrix}$

Replacing this derivative in the equation [Eq. 61] and using equation[Eq. 19]:

$\begin{matrix}{q_{inv} = {\frac{1}{L} \cdot {\int_{x_{s}}^{x_{d}}{{\left( {q_{im} + \left( {x_{m} - x} \right)} \right) \cdot \frac{L}{x_{ds}} \cdot \left( {1 + \frac{x_{m} - x}{q_{im}^{\prime}}} \right)}{dx}}}}} & \left\lbrack {{Eq}.\mspace{14mu} 67} \right\rbrack\end{matrix}$

With the integration:

$\begin{matrix}{q_{inv} = {\frac{1}{x_{ds}} \cdot \left\lbrack {{q_{im} \cdot {x\left( {\frac{q_{im}}{q_{im}^{\prime}} + 1} \right)} \cdot \frac{\left( {x - x_{m}} \right)^{2}}{2}} + \frac{\left( {x - x_{m}} \right)}{3 \cdot q_{im}^{\prime}}} \right\rbrack_{x_{s}}^{x_{d}}}} & \left\lbrack {{Eq}.\mspace{14mu} 68} \right\rbrack\end{matrix}$

Finally, the total normalized inversion charge is given by:

$\begin{matrix}{q_{inv} = {q_{im} + \frac{x_{ds}^{2}}{12 \cdot q_{im}^{\prime}}}} & \left\lbrack {{Eq}.\mspace{14mu} 69} \right\rbrack\end{matrix}$

Normalized Inversion Charge at the Drain Side q_(d)

For the calculation of the inversion charge at the drain side, themethod uses:

$\begin{matrix}{q_{d} = {\frac{1}{L} \cdot {\int_{0}^{L}{{q_{i} \cdot \frac{y}{L}}{dy}}}}} & \left\lbrack {{Eq}.\mspace{14mu} 70} \right\rbrack\end{matrix}$

Like for total inversion charge, this one can be calculated using thevariation of the surface potential along the channel:

$\begin{matrix}{q_{d} = {\frac{1}{L} \cdot {\int_{x_{s}}^{x_{d}}{{q_{i} \cdot \frac{y}{L} \cdot \frac{dy}{dx}}{dx}}}}} & \left\lbrack {{Eq}.\mspace{14mu} 71} \right\rbrack\end{matrix}$

The method uses a step of computing y/L.

Considering equation [Eq. 66], the method comprises a step ofintegrating between a position y along the channel and the positiony_(m) where the surface potential is equal to the mid-point surfacepotential x_(m) (equation f Eq. 211):

$\begin{matrix}{{\int_{y_{m}}^{y}{dy}} = {\int_{x_{m}}^{x}{{\frac{L}{x_{ds}} \cdot \left( {1 + \frac{x_{m} - x}{q_{im}^{\prime}}} \right)}\ {dx}}}} & \left\lbrack {{Eq}.\mspace{14mu} 72} \right\rbrack\end{matrix}$

After integration, we find:

$\begin{matrix}{\frac{y - y_{m}}{L} = {\frac{1}{x_{ds}} \cdot \left\lbrack {x - \frac{\left( {x - x_{m}} \right)^{2}}{2 \cdot q_{im}^{\prime}}} \right\rbrack_{x_{x}}^{x}}} & \left\lbrack {{Eq}.\mspace{14mu} 73} \right\rbrack\end{matrix}$

Finally,

$\begin{matrix}{\frac{y}{L} = {\frac{y_{m}}{L} + {\frac{1}{x_{ds}} \cdot \left( {x - x_{m} - \frac{\left( {x - x_{m}} \right)^{2}}{2 \cdot q_{im}^{\prime}}} \right)}}} & \left\lbrack {{Eq};\mspace{11mu} 74} \right\rbrack\end{matrix}$

The position y_(m) of the mid-point surface potential is obtainedconsidering the previous equation at the source side and at the drainside:

$\begin{matrix}{0 = {\frac{y_{m}}{L} + {\frac{1}{x_{ds}} \cdot \left( {x_{s} - x_{m} - \frac{\left( {x_{s} - x_{m}} \right)^{2}}{2 \cdot q_{im}^{\prime}}} \right)}}} & \left\lbrack {{Eq}.\mspace{14mu} 75} \right\rbrack \\{1 = {\frac{y_{m}}{L} + {\frac{1}{x_{ds}} \cdot \left( {x_{d} - x_{m} - \frac{\left( {x_{d} - x_{m}} \right)^{2}}{2 \cdot q_{im}^{\prime}}} \right)}}} & \left\lbrack {{Eq}.\mspace{14mu} 76} \right\rbrack\end{matrix}$

The sum of these two last equations gives:

$\begin{matrix}{{1 = {\frac{2 \cdot y_{m}}{L} + {\frac{1}{x_{ds}} \cdot \left( {x_{d} + x_{s} - {2 \cdot x_{m}} - \frac{\left( {x_{d} - x_{m}} \right)^{2}}{2 \cdot q_{im}^{\prime}} - \frac{\left( {x_{s} - x_{m}} \right)^{2}}{2 \cdot q_{im}^{\prime}}} \right)}}}\mspace{79mu}{{Thus},}} & \left\lbrack {{Eq}.\mspace{14mu} 77} \right\rbrack \\{\mspace{79mu}{y_{m} = {\frac{L}{2} \cdot \left( {1 + \frac{x_{ds}}{4 \cdot q_{im}^{\prime}}} \right)}}} & \left\lbrack {{Eq}.\mspace{14mu} 78} \right\rbrack\end{matrix}$

Back to the equation [Eq. 71] and using equations [Eq. 19], [Eq. 74] and[Eq. 66]:

$\begin{matrix}{q_{d} = {\frac{1}{L} \cdot {\int_{x_{s}}^{x_{d}}{{\left( {q_{im} + \left( {x_{m} - x} \right)} \right)\  \cdot \left( {\frac{y_{m}}{L} + {\frac{1}{x_{ds}} \cdot \left( {x - x_{m} - \frac{\left( {x - x_{m}} \right)^{2}}{2 \cdot q_{im}^{\prime}}} \right)}} \right) \cdot \frac{L}{x_{ds}} \cdot \left( {1 + \frac{x_{m} - x}{q_{im}^{\prime}}} \right)}{dx}}}}} & \left\lbrack {{Eq}.\mspace{14mu} 79} \right\rbrack \\{{q_{d} = {\frac{1}{x_{ds}^{2}} \cdot {\int_{x_{s}}^{x_{d}}{\left( {{A\; 0} + {A\;{1 \cdot \left( {x - x_{m}} \right)}} + {A\;{2 \cdot \left( {x - x_{m}} \right)^{2}}} + {A\;{3 \cdot \left( {x - x_{m}} \right)^{3}}} + {A\;{4 \cdot \left( {x - x_{m}} \right)^{4}}}} \right){dx}}}}}\mspace{79mu}{{With}\text{:}}\mspace{79mu}{{A\; 0} = {\frac{y_{m}}{L} \cdot q_{im} \cdot x_{ds}}}\mspace{79mu}{{A\; 1} = {{{- \frac{y_{m}}{L}} \cdot \left( {\frac{q_{im}}{q_{im}^{\prime}} + 1} \right) \cdot x_{ds}} + q_{im}}}\mspace{79mu}{{A\; 2} = {{\frac{y_{m}}{L} \cdot \frac{1}{q_{im}^{\prime}} \cdot x_{ds}} - \frac{q_{im}}{2 \cdot q_{im}^{\prime}} - \frac{q_{im}}{q_{im}^{\prime}} - 1}}\mspace{79mu}{{A\; 3} = {{\frac{1}{2 \cdot q_{im}^{\prime}} \cdot \left( {\frac{q_{im}}{q_{im}^{\prime}} + 1} \right)} + \frac{1}{q_{im}^{\prime}}}}\mspace{79mu}{{A\; 4} = {- \frac{1}{2 \cdot q_{im}^{\prime 2}}}}} & \left\lbrack {{Eq}.\mspace{14mu} 80} \right\rbrack\end{matrix}$

After integration, the equation [Eq. 80] becomes:

$\begin{matrix}{q_{d} = {{\frac{1}{x_{ds}^{2}} \cdot \left\lbrack {{A\;{0 \cdot x}} + {A\;{1 \cdot \frac{\left( {x - x_{m}} \right)^{2}}{2}}} + {A\;{2 \cdot \frac{\left( {x - x_{m}} \right)^{3}}{3}}} + {A\;{3 \cdot \frac{\left( {x - x_{m}} \right)^{4}}{4}}} + {A\;{4 \cdot \frac{\left( {x - x_{m}} \right)^{5}}{5}}}} \right\rbrack}\begin{matrix}x_{d} \\x_{s}\end{matrix}}} & \left\lbrack {{Eq}.\mspace{14mu} 81} \right\rbrack \\{\mspace{79mu}{{Thus},}} & \; \\{\mspace{79mu}{q_{d} = {\frac{1}{x_{ds}^{2}} \cdot \left( {{A\;{0 \cdot x_{ds}}} + {A\;{2 \cdot \frac{x_{ds}^{3}}{12}}} + {A\;{4 \cdot \frac{x_{ds}^{5}}{80}}}} \right)}}} & \left\lbrack {{Eq}.\mspace{14mu} 82} \right\rbrack\end{matrix}$

Replacing A0, A2 and A4 variables and using equation [Eq. 74], weobtain:

$\begin{matrix}{q_{d} = {\frac{1}{2}\left( {q_{im} - {\frac{x_{ds}}{6} \cdot \left( {1 - {\frac{x_{ds}}{2 \cdot q_{im}^{\prime}} \cdot \left( {1 + \frac{x_{ds}}{10 \cdot q_{im}^{\prime}}} \right)}} \right)}} \right)}} & \left\lbrack {{Eq}.\mspace{14mu} 83} \right\rbrack\end{matrix}$

Normalized Inversion Charge at the Source Side q_(s)

The inversion charge at the source side is:q _(s) =q _(inv) −q _(d)  [Eq. 84]

Normalized Gate Charge q_(g)

The inversion charge at the gate side is:q _(g) =q _(inv)  [Eq. 85]

One embodiment of the computer implemented method 200 of the inventionis illustrated on FIG. 17.

The method 200 comprises a first step 201 of measuring, severalgeometrical parameters such as the parameters presented in the table 1:the nanowires/nanosheet widths W_(W,i), the number of stackednanowires/nanosheets N_(W,i), the thickness of nanowires/nanosheetsH_(W,i), the physical gate oxide thickness T_(ox,p) and the cornerradius of nanowire/nanosheet R_(W,i). For this, transmission electronmicroscopy (TEM) may be used for instance. The first step may alsoinclude the measurement of the effective gate length L, for instance byusing a top view picture of the MOSFET.

The method 200 may further comprise a step 202 of measuring the totalgate capacitance value versus the gate voltage for several voltages witha drain voltage V_(DS) equal to zero. The gate voltage V_(GS) rangeshall beneficially cover all transistor regimes: weak inversion tostrong inversion. Such electrical measuring step is called C-Vmeasurements similarly to the one of FIG. 8(b). Capacitance-voltage C-Vmeasurement is a widely used method in microelectronics technology.

The method 200 may further comprise a step 203 of calculating, using aphysical processor and the above mentioned measured geometricalparameters, the normalized surface potential x as explained previouslyin the specification.

The method 200 may further comprise a step 204 of determining thenormalized inversion and gate charge as explained previously in thespecification (see for instance Equation 85).

The method 200 may further comprise a step 205 of calculating the totalgate capacitance based on the derivative of the gate charge previouslydetermined. Said calculation may be repeated for several gate voltagesin order to obtain a calculated total gate capacitance versus the gatevoltage for several voltages with a drain voltage V_(DS) equal to zero.

The method 200 may further comprise a step 206 of comparing thecalculated total gate capacitance obtained in step 205 with the measuredtotal gate voltage obtained in step 202.

The steps 203 to 206 may be repeated, for instance by varying the valueof the equivalent gate oxide T_(ox), in order to fit the calculatedtotal gate capacitance obtained in step 205 with the measured total gatevoltage obtained in step 202. Once the calculated total gate capacitanceobtained in step 205 and the measured total gate voltage obtained instep 202 are fitted, one can extract a value of the equivalent gateoxide T_(ox) that is very relevant.

Using the equivalent thickness gate oxide T_(ox) from the previous stepand the physical gate oxide thickness T_(ox,p) extracted from step 201,the physical gate oxide permittivity ε_(ox,p) can be obtained with thefollowing formula: ε_(ox,p)=ε_(ox)x(T_(ox,p)/T_(ox)) wherein ε_(ox) isrelative permittivity of SiO2 that may be considered as equal to 3.9.

Gate Capacitance Value Versus Gate Voltage:

As explained above, the method may comprise a step of determining thegate capacitance value versus the gate voltage. This step enables tocompare the results obtained by the method according to one embodimentof the invention and the results obtained by numerical simulations suchas TCAD (Technology Computer Aided Design) simulations.

FIGS. 4(a) to 15(b) represents comparison between the results obtainedby the method according to one embodiment of the invention and numericalsimulations, for different shapes of stacked nanowire MOSFET. As we cansee, the results obtained by the two methods are very similar.

While the present invention has been particularly described withreference to the preferred embodiments, it should be readily apparent tothose of ordinary skill in the art that changes and modifications inform and details may be made without departing from the scope of theinvention.

What is claimed is:
 1. A computer implemented method for designing anintegrated circuit that includes a stacked nanowires/nanosheetsgate-all-around (GAA) metal oxide semiconductor field effect transistor(MOSFET) comprising N_(w) nanowires and/or nanosheets, eachnanowire/nanosheet being surrounded in an oxide layer, the oxide layersbeing embedded in a common gate, wherein the method comprises thefollowing steps: determining at least one intrinsic parameter of thestacked nanowires/nanosheets gate-all-around (GAA) metal oxidesemiconductor field effect transistor (MOSFET) by: measuring by at leastone imaging method using a microscopy device the following geometricalparameters of the MOSFET: the number of stacked nanowires/nanosheetsN_(W), the width W_(W,i), of the nanowire/nanosheet number i, i being aninteger from 1 to N_(W), the thickness of the nanowire/nanosheetH_(W,i), number i, i being an integer from 1 to N_(W), the corner radiusR_(W,i) of the nanowire/nanosheet number i, i being an integer from 1 toN_(W), R_(W,i); calculating, using a physical processor and the measuredgeometrical parameters, a surface potential x normalized by a thermalvoltage ϕ_(T) given by ϕ_(T)=k_(B)T/q; measuring electrically the totalgate capacitance for a plurality of gate voltages; determining, usingthe measured total gate capacitance and the calculated normalizedsurface potential, the at least one intrinsic parameter of the stackednanowires/nanosheets MOSFET, reproducing, based on said at least oneintrinsic parameter, electrical characteristics in all biasing of thestacked nanowires/nanosheets gate-all-around (GAA) metal oxidesemiconductor field effect transistor (MOSFET), determining electricalproperties of the integrated circuit based on the reproduced electricalcharacteristics, and optimizing a device architecture of the integratedcircuit with regard to consumption, performance and surface technologytargets based on the determined electrical properties.
 2. A computerimplemented method according to claim 1, wherein the normalized surfacepotential x satisfies the following equation:(x _(g) −x)² +B _(sp)·(x _(g) −x)=Δ_(f)·exp(x−x _(n)) Where B_(sp) andΔ_(f) are constants depending on the geometry of the stackednanowires/nanosheets MOSFET and x_(g) is an effective gate bias.
 3. Acomputer implemented method according to claim 2, further comprising astep of determining, using a physical processor, constants B_(sp) andΔ_(f) according to geometry parameters of the stackednanowires/nanosheets GAA MOSFET and process parameters, wherein the stepof determining constants B_(sp) and Δ_(f) comprises a step of:determining, for each nanowire, using a physical processor, an effectivechannel width W_(effnw,i) corresponding to a perimeter of a transversalsection of the nanowire/nanosheet; determining, for each oxide layer,using a physical processor, an effective oxide width W_(effox,i)corresponding to an exterior perimeter of a transversal section of theoxide layer.
 4. A computer implemented method according to claim 3,wherein the step of determining constants B_(sp) and Δ_(f) furthercomprises a step of: determining, for each oxide layer, using a physicalprocessor, an equivalent normalized gate oxide capacitance C_(oxnw,i)given by:$C_{{oxnw},i} = {\frac{ɛ_{ox}}{T_{ox}} \cdot \frac{W_{{oxnw},i}}{W_{{effnw},i}}}$Where ε_(ox) is a dielectric permittivity of the gate and T_(ox) is aneffective gate dielectric equivalent oxide thickness.
 5. A computerimplemented method according to claim 4, wherein the step of determiningconstants B_(sp) and Δ_(f) further comprises a step of determining,using a physical processor, a total equivalent gate oxide capacitanceC_(ox)′ given by:$C_{ox}^{\prime} = {\sum\limits_{i = 1}^{N_{w}}\;{\frac{W_{{effnw},i}}{\sum\limits_{i = 1}^{N_{w}}\; W_{{effnw},i}} \cdot {C_{{oxnw},i}^{\prime}.}}}$6. A computer implemented method according to claim 3, wherein the stepof determining constants B_(sp) and Δ_(f) further comprises a step ofDetermining, using a physical processor, an equivalent semiconductorfilm thickness H_(spnw,i) given by:$H_{{spnw},i} = {{\frac{2 \cdot \left( {W_{W,i} - H_{W,i}} \right)}{W_{{effnw},i}} \cdot H_{W,i}} + {\frac{{2 \cdot \pi \cdot R_{c,i}} + {4 \cdot \left( {H_{W,i} - {2 \cdot R_{c,i}}} \right)}}{W_{{effnw},i}} \cdot \frac{2 \cdot H_{W,i}}{\pi} \cdot \left( {{\ln\left( {1 - {2 \cdot \frac{R_{c,i}}{H_{W,i}}} + \sqrt{1 + \left( {1 - {2 \cdot \frac{R_{c,i}}{H_{W,i}}}} \right)^{2}}} \right)} + {{\frac{\sqrt{1 + \left( {1 - {2 \cdot \frac{R_{c,i}}{H_{W,i}}}} \right)^{2}} + {2 \cdot \left( {{\left( {\sqrt{2} - 1} \right) \cdot \left( {1 - {2 \cdot \frac{R_{c,i}}{H_{W,i}}}} \right)} + 1} \right)}}{3} \cdot {a\tan}}\left( \frac{\frac{R_{c,i}}{H_{W,i}}}{1 - \frac{R_{c,i}}{H_{W,i}}} \right)}} \right)}}$Where H_(w,i) is an effective thickness of the nanowire i, W_(w,i) is aneffective width of the nanowire i R_(c,i) is an effective corner radiusof the nanowire i.
 7. A computer implemented method according to claim6, wherein the step of determining constants B_(sp) and Δ_(f) furthercomprises a step of determining, using a physical processor, a totalequivalent film thickness H_(sp) given by$H_{sp} = {\sum\limits_{i = 1}^{N_{w}}\;{\frac{W_{{effnw},i}}{\sum\limits_{i = 1}^{N_{w}}\; W_{{effnw},i}} \cdot {H_{{spnw},i}.}}}$8. A computer implemented method according to claim 5, wherein the stepof determining constants B_(sp) and Δ_(f) further comprises a step ofcomputing, using a physical processor, B_(sp) such that$B_{sp} = \frac{4 \cdot ɛ_{ch}}{H_{sp} \cdot C_{{ox}^{\prime}}}$ Whereε_(ch) is a channel dielectric permittivity.
 9. A computer implementedmethod according to claim 5, wherein the step of determining constantsB_(sp) and Δ_(f) further comprises a step of computing, using a physicalprocessor, Δ_(f) such that$\Delta_{f} = \frac{2 \cdot q \cdot n_{ch} \cdot ɛ_{ch}}{\phi_{T} \cdot C_{ox}^{\prime 2}}$Where q is an elementary charge, n_(ch) is an intrinsic channel dopingconcentration, □_(ch) is a channel dielectric permittivity, ϕ_(T) is athermal voltage given by ϕ_(T)=k_(B)T/q.
 10. A computer implementedmethod according to claim 1, further comprising a step of determining,using a physical processor, a channel current according to the surfacepotential.
 11. A computer implemented method according to claim 1,further comprising a step of determining, using a physical processor, agate charge according to the surface potential.
 12. A computerimplemented method according to claim 11, further comprising a step ofdetermining the total gate capacitance value according to the determinedgate charge and a step of comparing the determined total gatecapacitance value with the electrically measured total gate capacitance,said comparison being carried out with a plurality of gate voltages. 13.A computer implemented method according to claim 1, wherein the at leastone imaging method includes a direct measurement of geometricalcharacteristics using one or more images via transmission electronmicroscopy.
 14. A computer implemented method according to claim 1,wherein the electrical properties of the integrated circuit includepower consumption.